Senior Engineer, Digital Design Engineering for Analog Devices, Inc. in Colorado Springs, CO to:

Work with digital and analog designers, algorithm engineers and software developers to implement state-of-the-art mixed-signal technology ASICs. Collaborate with design teams and software /firmware development teams to capture the intended operation and configuration of the system. Collaborate with other digital design engineers to code the design in System Verilog RTL. Integrate 3rd party IP, such as micro-controller cores, non-volatile memories, and communication interfaces, and identify relevant test cases. Perform RTL and gate-level simulation debug and analysis. Support implementation engineers throughout the back-end tool flow to help debug issues, insert and simulate scan tests, and reach timing closure. Verify designed block logic circuit functionality by writing both block and sub-block level test-benches and regression tests. Consult with digital verification engineers to develop System Verilog UVM simulation environments, infrastructure and verification plans at both full chip and block level. Assist verification engineers to create, simulate and debug constrained random and directed cases based on the verification plans. Write functional coverage, assertions, and other metrics to track progress and completeness of verification effort. Conduct regressions analyses, including debugging of circuit failures in regression testing. Run structural simulations with post-layout timing information. Support verification engineers to analyze coverage results and take necessary actions to fill the coverage gaps.

Partial telecommute benefit (2 days WFH/week).

Requirements: Master's degree in Electrical Engineering or a related field of study (willing to accept a foreign education equivalent) plus two (2) years of experience as an Electrical Engineer or related occupation performing Digital Logic Design and Verification Engineering.

Specific skills/other requirements - Must also possess the following (quantitative experience requirements not applicable to this section):

Demonstrated Expertise (DE) writing Constrained Random and Directed test sequences as part of Pre-Silicon System Verilog testing, to target functional coverage items based on the test plan and datasheet; DE designing and writing readable, logical and functionally accurate, pipelined RTL modules in Verilog using best design practices, then using synthesis and other backend tools and methods to meet power, performance, and timing specifications; DE confirming test intentions and code accuracy through schematic review; and debugging using RTL simulation waveforms (using Verdi), and generated log and tracker files; and re-coding tests for sequential coherency; DE developing and revamping UVM based verification testbench, while adding more randomization to test sequences for targeting of newer features, and updating the predictor, scoreboard and coverage components pertaining to block and subsystem-level environments; and DE working directly with computer architecture circuits including caches, branch predictors, pipelines, and execution units.

Eligible for employee referral program. Apply online at https://www.analog.com/en/about-adi/careers.html and Reference Position Number: R241545. Salary: $95,971.00 - $150,670.00.